The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to a multideposition sub-atmospheric chemical vapor deposition (SACVD) reactor enabling the rapid thermal deposition of dielectric materials such Si3N4, SiO2, and SiON and of non-dielectric materials such as polysilicon onto a substrate. According to the present invention, said dielectric/non-dielectric materials can be now deposited according to the desired sequence in the same chamber of the multideposition SACVD reactor, significantly reducing cycle time, total thermal budget and pattern factor effects.
Short cycle time and low thermal budget are certainly the most critical points for Application Specific Integrated Circuit (ASIC) and Dynamic Random Access Memory (DRAM) products manufacturing respectively. The continuous technical progress in the last decades has resulted in the emergence of new techniques to improve product integration and speed that shows out the necessity to work deeper on deposition tool to improve their characteristics. Requirements such as low thermal budget, low pattern factor, foreign element control and short cycle time are now becoming of paramount importance. A low thermal budget is essential to keep IGFET effective channel length (Leff) within specifications, to increase the process window and to have low junction contact resistance. Another important parameter is the pattern factor which is determining to embed memory cells in a logic chip. Still another parameter (previously deemed more secondary) is the foreign element control. Foreign elements that are incorporated into the deposited films during fabrication also drive device performance, and thus are becoming more important to date, as devices become more and more dense and complex. The possibility to control foreign element presence in deposited films facilitates the tuning of the devices and the correction or adjustment of some electrical fails such as junction leakages and the retention time. Finally, short cycle times which increase the manufacturing throughput are also worthwhile in terms of cost reduction. All these parameters have become critical in semiconductor devices particularly when it is required to deposit dielectric and non-dielectric materials in sequence according to the Chemical Vapor Deposition (CVD) technique. It would be highly desirable to perform the maximum deposition steps in the same equipment without unloading the wafers in order to improve the manufacturing throughput and to reduce the cycle time.
In the course of fabricating IGFETs for a standard DRAM product, at the stage of the gate conductor formation, it is required to form a stack (GC stack) comprised of a bottom 10 nm thick SiO2 gate layer, then a 80 nm thick doped polysilicon layer, a 70 nm thick tungsten silicide (WSix) layer and finally a 180 nm thick top protective cap Si3N4 layer. Next, the GC stack is patterned by dry etching to produce the gate conductor lines (GC lines) and a thin SiO2 spacer is formed by thermal oxidation on the exposed sidewalls of the doped polysilicon material. All these processing steps are performed in a different tool in the so-called Middle End Of the Line (MEOL) module.
For instance, the thin SiO2 bottom gate layer is obtained by thermal oxidation using an Atmospheric Pressure Oxidation furnace (APOX) as standard, such as the SVG VTR 7000 (oxidation) vertical furnace sold by SVG-THERMCO, San Jose, Calif., USA. The deposition of the 80 nm thick doped polysilicon layer and the 70 nm thick WSix layer is performed in two different chambers of a SACVD Centura HTF reactor, a tool manufactured by Applied Materials Inc, Santa Clara, Calif., USA using the following operating conditions:
Doped Polysilicon Deposition
wherein xe2x80x9csccmxe2x80x9d denotes standard cubic centimers per minute and xe2x80x9cslmxe2x80x9d denotes standard liters per minute.
WSix Deposition
Finally, the Si3N4 material is deposited in a LPCVD batch furnace, such as a TEL Alpha 8s, a tool sold by TOKYO ELECTRON Ltd, Tokyo, Japan using the operating conditions recited below.
Si3N4 Deposition
Step 1
Step 2
The first step must be conducted at a low temperature to prevent WSix oxidation at boat insertion in the furnace. About 100 wafers are processed for a total time (including loading/unloading operations) of about 375 min.
TABLE I below summarizes this sequence of deposition steps that are performed in the MEOL module.
More generally, if we consider all processing steps that are performed in the DRAM manufacturing line, the use of LPCVD and APOX furnaces are substantially limited to the Front End Of the Line (FEOL) and MEOL modules, as summarized in TABLE II below, for the deposition for different types of materials.
(1) and (2) respectively refer to the duration for LPCVD/APOX and SACVD processes. There is no breakdown when the wafer is moved from chamber 1 to chamber 2 of the SACVD tool but there is a significant breakdown after the wafer is unloaded from chamber 2 to be loaded in the LPCVD furnace. Because, the LPCVD tool is of the batch type, there is an important wait time before a full batch of 100 wafers is loaded. As a consequence, before inserting the boat in the furnace, the wafers need to be cleaned for instance in a FSI spray tool (FLUOROWARE SYSTEMS Inc., Minneapolis, USA) using a SP/Huang AB cleaning sequence. As a whole, these operations are time consuming.
It is not possible to deposit the Si3N4 material in the same AME Centura reactor because processing chambers are strictly limited to the deposition of polysilicon films or WSix films.
Applicants have discovered a manner to modify this conventional SACVD reactor normally exclusively used to perform polysilicon deposition to add the capacity of depositing dielectric materials such as Si3N4, SiON and SiO2 in addition to polysilicon. As a result, multideposition of materials as different as dielectric and polysilicon in the reactor chamber according to any desired sequence is now possible without the above mentioned inconveniences (wait time, cleaning and long cycle time).
It is therefore a primary object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a substrate in the same chamber of the reactor.
It is another primary object of the present invention to provide a multideposition CVD reactor provided with multiple chambers enabling the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a substrate in two dedicated chambers of the reactor.
It is another object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a substrate that is particularly adapted to ASIC production (short cycle times and low thermal budget).
It is another object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a substrate that is provided with an improved susceptor and a gas distribution system adapted to multiple material deposition.
It is another object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a substrate that allows high throughput.
It is another object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a substrate that can be widely used elsewhere in the manufacturing line irrespective the module (FEOL/MEOL).
It is still another object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a substrate that is well adapted to the fabrication of borderless polysilicon contacts in advanced EDRAM/SDRAM silicon chips.
It is still another further object of the present invention to provide a multideposition CVD reactor enabling the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a substrate that is well adapted to fully integrate the GC stack fabrication process in advanced SDRAM silicon chips.
According to the present invention there is described a multideposition sub-atmospheric chemical vapor deposition (SACVD) reactor comprising: a substrate processing chamber; a carbon susceptor adapted to hold a substrate in said substrate processing chamber during a SACVD operation, wherein said carbon susceptor is coated by a polysilicon film to protect it against said cleaning gases; a gas distribution system adapted to introduce gases into said substrate processing chamber and including appropriate valves, gas supply lines and other equipment necessary to flow gases into the substrate processing chamber; wherein said gases include dielectric/non-dielectric forming gases and in-situ cleaning gases that are aggressive to carbon; a heating system to heat the susceptor/wafer to the adequate deposition temperature; a pressurization system adapted to set a pressure level within said substrate processing chamber; and a controller coupled to said gas distribution system and pressurization system for directing the operation of the SACVD reactor.
When the SACVD Centura reactor is used as the base deposition tool, the present invention also concerns the method of coating said carbon plate in the case, the dielectric material to be deposited is Si3N4 to render it NF3 resistant, said method comprising the steps of: a) placing the standard carbon susceptor in the reactor processing chamber; b) cleaning the chamber interior volume with HCl; c) purging said interior volume with H2; d) coating the susceptor bottom with a film of polysilicon using a DCS precursor; e) purging said interior volume with H2; f) coating the susceptor top with a film of polysilicon using a SiH4 precursor; and g) purging said interior volume with H2.
A multideposition process is now made possible with tools that are provided with multiple chambers, such as the AME Centura HTF reactor, wherein every chamber can be dedicated to the deposition of a single material (dielectric or polysilicon) for a totally integrated process (cluster mode).
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.